1. Field of the Invention
The present invention relates generally to the packaging of integrated circuits. More particularly, the present invention relates to a method and apparatus for providing high density chips on a printed circuit board or other substrate using leadless leadframe packages.
2. Description of the Related Art
A leadless lead frame package (LLP) is an integrated circuit package design that contemplates the use of a lead frame in the formation of a chip scale package (CSP). The resulting packages are sometimes referred to as quad flat packsxe2x80x94no lead (QFN) packages. As illustrated in FIG. 1, in typical leadless lead frame packages, a copper lead frame strip or panel 101 is patterned (typically by stamping or etching) to define a plurality of arrays 103 of chip substrate features 105. Each chip substrate feature 105 includes a die attach pad 107 and a plurality of contacts 109 disposed about their associated die attach pad 107. Very fine tie bars 111 are often used to support the die attach pads 107 and contacts 109.
During assembly, dice are attached to the respective die attach pads and conventional wire bonding is used to electrically couple bond pads on each die to their associated contacts 109 on the lead frame strip 101. After the wire bonding, a plastic cap is molded over the top surface of the each array 103 of wire bonded dice. The dice are then singulated and tested using conventional sawing and testing techniques.
FIG. 2 illustrates a typical resulting leadless lead frame package. The die attach pad 107 supports a die 120 which is electrically connected to its associated contacts 109 by bonding wires 122. A plastic casing 125 encapsulates the die 120 and bonding wires 122 and fills the gaps between the die attach pad 107 and the contacts 109 thereby serving to hold the contacts in place. It should be appreciated that during singulation, the tie bars 111 are cut and therefore the only materials holding the contacts 109 in place is the molding material. The resulting packaged chip can then be surface mounted on a printed circuit board or other substrate using conventional techniques.
Since leadless lead frame packaging have proven to be a cost effective packaging arrangement, there are continuing efforts to provide further improvements to the package structure and/or processing to permit the package style to be used in additional applications and/or to improve specific characteristics of the resultant devices.
To achieve the foregoing and other objects and according to the purpose of the present invention, a variety of improved packaging arrangements are disclosed. A semiconductor package is provided with an internal package formed in the cavity of the external leadless leadframe package (LLP). The internal package is a leadless leadframe package and provides a substrate for mounting one or more die and passive devices to form the external LLP. By arranging the die and passive components on the internal package, higher chip density and a smaller form factor may be achieved. Moreover, better electrical performance results from the shorter trace lengths.
In one embodiment, a semiconductor package includes an internal package having a first plurality of contacts. The first plurality of contacts is exposed on a first surface of the internal package. The internal package further includes a first die electrically connected to at least some of the first plurality of contacts. The internal package further includes a first molding material that encapsulates the first die. The semiconductor package further includes a leadframe having a second plurality of contacts. A second die is mounted on the internal package and electrically connected to the second plurality of contacts. A second molding material is provided and encapsulates the second die and a portion of the internal package.
In another embodiment, multiple dies are arranged on the internal package and connected by wire bonds to contacts at the periphery of the external semiconductor package.
These and other features and advantages of the present invention are described below with reference to the drawings.